View 82C283_2994292.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

82C283 september 1994 opti inc. 2525 walsh avenue santa clara, ca 95051 (408) 980-8178 386sx system controller opti ? 1.0 features ? flexible dram banks configuration - supports 256k, 1m and 4m dram ? block interleave mode operations - block interleaving at a block size of 512 bytes ? bios shadow ram - shadow ram for system, video and adapter bios ? memory remapping ? flexible multiplexed dram address ? programmable at bus clock ? turbo switch ? 160-pin pqfp (plastic quad flat pack) 2.0 overview the 82C283 is a highly integrated, at system logic vlsi chip for high-end 386sx/at systems. it integrates a local memory controller (local memory is on-board memory), at bus con- troller, and data bus controller into one chip. it is designed for systems running at 16mhz, 20mhz, 25mhz, and 33mhz*. a high performance, compact 386sx/at system is readily implemented with the 82C283 and a standard peripheral con- troller like optis 82c206 or the 82c100 (with dallas semi- cond uctor (ds1287). *rev. b only figure 2-1 system block diagram opti 82C283 d bus 245 245 ga20 xa0 dram 387sx 386sx 245 rom 8042 a bus a[16:1] a[23:17] a[9:1] a[23:16] ras, cas, sd[15:0] sa[19:17] sa[16:0] la[23:17] xd[7:0] sa sd opti 82c206 xd[7:0] sd bus ma sa bus d[15:0] d[15:0] a[23:0] (x2)
82C283 page 2 912-3000-012 opti ? 3.0 signal definitions figure 3-1 pin diagram 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 gnd gnd sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 m16# xdir# out2 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 clki gnd gnd 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 gnd gnd ma6 ma7 ma8 ma9 ma10 ras3# ras2# ras1# ras0# cas7# cas6# cas5# cas4# cas3# cas2# cas1# cas0#i dwe# romcs# chck# chrdy preqi preqo spkd gate2 turbo mp0 mp1 d0 d1 d2 d3 d4 d5 d6 d7 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vcc d8 d9 d10 d11 d12 d13 d14 d15 hlda hold ads# mio# dc# wr# rdy# bhe# osc gnd vcc gnd pclk2 nmi cpurst smwr# ga20 busy# npint nperr# npbusy# nprst rdyi# na# smrd# ads16 ads8 sa19 sa18 sa17 vcc vcc ma5 ma4 ma3 ma2 ma1 ma0 hrq dma8# dma16# hlda1 io16# asrtc ale kbdcs# xa0 osc12 rfsh# atclk gnd vcc gnd sbhe# memrd# memwr# iord# iowr# inta# pwrgd# bufcon# sysrst sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 vcc 82C283 system controller
82C283 912-3000-012 pa ge 3 opti ? table 3-1 numerical pin cross-reference list pin no. pin name 1 vcc 2d8 3d9 4 d10 5 d11 6 d12 7 d13 8 d14 9 d15 10 hlda 11 hold 12 ads# 13 mio# 14 dc# 15 wr# 16 rdy# 17 bhe# 18 osc 19 gnd 20 vcc 21 gnd 22 pclk2 23 nmi 24 cpurst 25 smwr# 26 ga20 27 busy# 28 npint 29 nperr# 30 npbusy# 31 nprst 32 rdyi# 33 na# 34 smrd# 35 ads16 36 ads8 37 sa19 38 sa18 39 sa17 40 vcc 41 gnd 42 gnd 43 clki 44 a0 45 a1 46 a2 47 a3 48 a4 49 a5 50 a6 51 a7 52 a8 53 a9 54 a10 55 a11 56 a12 57 a13 58 a14 59 a15 60 a16 61 a17 62 a18 63 a19 64 a20 65 a21 66 a22 67 a23 68 out2 69 xdir# 70 m16# 71 sd15 72 sd14 73 sd13 74 sd12 75 sd11 76 sd10 77 sd9 78 sd8 79 gnd 80 gnd pin no. pin name 81 vcc 82 sd7 83 sd6 84 sd5 85 sd4 86 sd3 87 sd2 88 sd1 89 sd0 90 sysrst 91 bufcon# 92 prwgd# 93 inta# 94 io wr# 95 iord# 96 memwr# 97 memrd# 98 sbhe# 99 gnd 100 vcc 101 gnd 102 atclk 103 rfsh# 104 osc12 105 xa0 106 kbdcs# 107 ale 108 asrtc 109 io16# 110 hlda1 111 dma16# 112 dma8# 113 hrq 114 ma0 115 ma1 116 ma2 117 ma3 118 ma4 119 ma5 120 vcc pin no. pin name 121 gnd 122 gnd 123 ma6 124 ma7 125 ma8 126 ma9 127 ma10 128 ras3# 129 ras2# 130 ras1# 131 ras0# 132 cas7# 133 cas6# 134 cas5# 135 cas4# 136 cas3# 137 cas2# 138 cas1# 139 cas0# 140 dwe# 141 romcs# 142 chck# 143 chrdy 144 preqi 145 preqo 146 spkd 147 gate2 148 turbo 149 mp0 150 mp1 151 d0 152 d1 153 d2 154 d3 155 d4 156 d5 157 d6 158 d7 159 gnd 160 gnd pin no. pin name
82C283 page 4 912-3000-012 opti ? table 3-2 alphabetical pin cross reference list pin name pin no. a0 44 a1 45 a2 46 a3 47 a4 48 a5 49 a6 50 a7 51 a8 52 a9 53 a10 54 a11 55 a12 56 a13 57 a14 58 a15 59 a16 60 a17 61 a18 62 a19 63 a20 64 a21 65 a22 66 a23 67 ads# 12 ads8 36 ads16 35 ale 107 asrtc 108 atclk 102 bhe# 17 bufcon# 91 busy# 27 cas0# 139 cas1# 138 cas2# 137 cas3# 136 cas4# 135 cas5# 134 cas6# 133 cas7# 132 chck# 142 chrdy 143 clki 43 cpurst 24 d0 151 d1 152 d2 153 d3 154 d4 155 d5 156 d6 157 d7 158 d8 2 d9 3 d10 4 d11 5 d12 6 d13 7 d14 8 d15 9 dc# 14 dma8# 112 dam16# 111 dwe# 140 ga20 26 gate2 147 gnd 19 gnd 21 gnd 41 gnd 42 gnd 79 gnd 80 gnd 99 gnd 101 gnd 121 gnd 122 gnd 159 gnd 160 hlda 10 pin name pin no. hlda1 110 hold 11 hrq 113 inta# 93 io16# 109 iord# 95 iowr# 94 kbdcs# 106 m16# 70 ma0 114 ma1 115 ma2 116 ma3 117 ma4 118 ma5 119 ma6 123 ma7 124 ma8 125 ma9 126 ma10 127 mio# 13 mp0 149 mp1 150 memrd# 97 memwr# 96 na# 33 nmi 23 npbusy# 30 nperr# 29 npint 28 nprst 31 osc 18 osc12 104 out2 68 pclk2 22 preqi 144 preqo 145 prwgd# 92 ras0# 131 ras1# 130 pin name pin no. ras2# 129 ras3# 128 rdy# 16 rdyi# 32 rfsh# 103 romcs# 141 sa19 37 sa18 38 sa17 39 sbhe# 98 sd0 89 sd1 88 sd2 87 sd3 86 sd4 85 sd5 84 sd6 83 sd7 82 sd8 78 sd9 77 sd10 76 sd11 75 sd12 74 sd13 73 sd14 72 sd15 71 smrd# 34 smwr# 25 spkd 146 sysrst 90 turbo 148 vcc 1 vcc 20 vcc 40 vcc 81 vcc 100 vcc 120 wr# 15 xdir# 69 xa0 105 pin name pin no.
82C283 912-3000-012 pa ge 5 opti ? 3.1 signal descriptions 3.1.1 clock and reset interface signals 3.1.2 cpu control and interface signals signal name pin no. signal type signal description clki 43 i clk2 i nput from oscillator. pclk2 22 i/o clk2 out put to 386sx and 387sx. (bidirectional output is always enabled.) osc12 104 o 1.19mhz output. osc 18 i 14.31818mhz oscillator input. signal name pin no. signal type signal description a[23:17] 67:61 i cpu address bus: address lines 23 through 17 and 7 through 0. a[16:8] 60:52 i/o cpu address bus: address lines 16 through 8. these signals are inputs except during dma cycles. a[16:9] become outputs and convey dma address 16-9 for 16-bit dma cycles. a[15:8] become outputs and convey dma address 15-8 for 8- bit dma cycles. a[10:9] are outputs during refresh. a[7:0] 51:44 i/o cpu address bus: address lines 7 through 0. these inputs become outputs dur- ing refresh. d[15:0] 9:2, 158:151 i/o data bus to/from the cpu. mp[1:0] 150, 149 i/o local dram parity bits 1 and 0. rdyi# 32 i ready input from coprocessor ready. rdy# 16 o ready output to the cpu to terminate the current cycle. na# 33 o cpu next address control signal. cpurst 24 o cpu reset si gnal. nmi 23 o non-maskable interrupt. wr# 15 i write or read is a bus cycle definition pin that distinguishes write cycles from reads cycles. dc# 14 i data or control is a bus cycle definition pin that distinguishes data cycles from control cycles. mio# 13 i memory or i/o is a bus cycle definition pin that distinguishes memory cycles from input/output cycles. ads# 12 i address status from the 386sx. hold 11 o hold r equest to the 3 86sx hlda 10 i hold ack nowledge from the 286sx. bhe# 17 i/o byte high enable f rom the cpu. it is an input during cpu cycles and an output during non-cpu cycles.
82C283 page 6 912-3000-012 opti ? signal descriptions (cont.) 3.1.3 dram interface signals 3.1.4 at bus interface signals signal name pin no. signal type signal description ras[3:0]# 128:131 o local dram row address strobe signals. cas[7:0]# 132:139 i local dram column address strobe signals. ma[10:0] 127:123, 119:114 o multiplexed row and column address bits 10 through 0. rfsh# 103 i/o refresh cycle indication signal. dwe# 140 o dram write/read control signal. signal name pin no. signal type signal description ale 107 t at bus address latch enable. this signal is tristated during master cycles. xa0 105 i/o system board latched address bit 0. this signal is an output for cpu, refresh, or 16-bit dma cycles and an input for 8-bit dma or master cycles. atclk 102 o at system clock, atclk = clk2/6 (default), atclk can be set to clk2/4 by programming the internal registers. sbhe# 98 i/o system byte high enable to/from the at bus. sbhe# is an input during master cycles. memrd# 97 i/o me mory read comm and signal. memwr# 96 i/o me mory write command signal. iord# 95 i/o i/o read command signal. iowr# 94 i/o i/o write command signal. chrdy 143 i i/o channel ready signal from the at channel. io16# 109 i i/o data size 16 indication from at cha nnel. m16# 70 i/o me mory data size 16 indication f rom the at channel. chck# 142 i channel check signal f rom the at channel. sa[19:17] 37:39 o system address lines 19 through 17. tristated during master cycles. smrd# 34 o at memory read command to memory below 1mb. smwr# 25 o at memory write command to me mory below 1mb sd[15:0] 71:78, 82:89 i/o system data bus lines 15 through 0. these si gnals are c onnected to at data bus directly.
82C283 912-3000-012 pa ge 7 opti ? signal descriptions (cont.) 3.1.5 dma interface signals 3.1.6 miscellaneous interface signals 3.1.7 numeric coprocessor interface signals signal name pin no. signal type signal description dma8# 112 i 8-bit dma transfer indication. dma16# 111 i 16-bit dma transfer indication. hrq 113 i hold request from the 82c206 ipc. hlda1 110 o hold ack nowledge 1 indicates a cpu hlda was caused by hrq, not by a refresh request. ads8 36 i 8-bit dma transfer address strobe. ads16 35 i 16-bit dma transfer address strobe. signal name pin no. signal type signal description kbdcs# 106 o i/o port 60 and 64 address decode. it is de-activated during dma cycles. turbo 148 i turbo switch control. cpuclk2 = atclk2 if turbo pin is low when turbo switch function is enabled. gate2 147 o timer 2 enable si gnal. spkd 146 o speaker output. inta# 93 o inter rupt acknowledge cycle indication. pwrgd# 92 i power bad indication. sysrst 90 o system reset signal. romcs# 141 o bios rom output e nable signal ga20 26 i/o gate address 20. it is an input from master card during master cycles. con- nected to at bus la20 indirectly through a buffer. xdir# 69 o xd bus to/from sd bus direction control. asrtc 108 o address st robe for real-time clock. bufcon# 91 o buffer control signal. bufcon# goes low during a master and non-refresh cycle. out2 68 i timer 2 output. signal name pin no. signal type signal description npbusy# 30 i numeric coprocessor busy signal. nperr# 29 i numeric coprocessor error signal. nprst 31 o numeric coprocessor reset.
82C283 page 8 912-3000-012 opti ? signal descriptions (cont.) 3.1.8 power and ground pins npint 28 o interrupt request 13 for 387sx exception. busy# 27 o numeric c oprocessor busy and error status to cpu busy input. preqo 145 o connected to the 386sx preq input. preqi 144 i connected to the 387sx preq output. signal name pin no. signal type signal description vcc 1, 20, 40, 81, 100, 120 i power connection: +5.0v gnd 19, 21, 41, 42, 79, 80, 99, 101, 121, 122, 159, 160 i ground connection signal name pin no. signal type signal description
82C283 912-3000-012 pa ge 9 opti ? 4.0 functional description the following sub-sections will explain the various cycles, features, and operations of the 82C283. 4.1 local memory controller the 82C283 memory controller has the following fea tures: ? flexible dram banks configuration - the 82C283 sup- ports 256k, 1m, and 4m size dram. total memory can be up to 16mb. twelve me mory confi gurations are supported as shown in table 4-1. ? block interleave mode operations - depending on the memory configurati on, the local memory controller unit performs block interleaving at a block size of 512 bytes using 256k, 1m or 4m drams. ? bios shadow ram - the local me mory c ontroller can shadow ram for system bios, video bios, and adapter bios. - 0f0000h-0fff ffh is system bios area and can be programmed to be: - read during at rom cycles; written during local memory cycles (default). - read during local memory cycles with no writes allowed (write-protected). - 0c000h-0effffh contains twelve 16kb blocks, e ach programmable: - read from at bus; write to at bus (default). - read from at bus; write to local memory. - read from local memory; write to local memory. - read from local memory and write protected. ? memory remapping - if shadow ram is not used at mem- ory area 0d0000h-0effffh, remapping is possible. then, local memory areas 0a0000h-0bffffh and 0d0000h- 0effffh (each 128k bytes) are mapped to the top of total memory. memory areas 0f0000h-0fffffh (system bios) and 0 c0000h-0cffffh (video bios) are reserved for shadow ram. ? flexible multiplexed dram address - table 4-2 s hows how dram address lines are multiplexed when different size dram are used. table 4-1 dram banks configurations *rev. b only bank 0 bank 1 bank 2 bank 3 total 256k 256k 1m 256k 256k 256k 256k 2m 1m 2m 256k 256k 1m 3m 1m 1m 4m 256k 256k 1m 1m 5m 1m 1m 1m 6m 1m 1m 1m 1m 8m 256k 256k 4m 9m 1m 4m 10m 1m 1m 4m 12m 4m 4m 16m 4m* 8m table 4-2 address to ma mapping memory address 256k 1m 4m col row col row col row 0 111120120 1 212211222 2 313312312 3 414413413 4 515514514 5 616615615 6 717716716 7 818817817 8 101910181018 9919919 10 11 21
82C283 page 10 912-3000-012 opti ? 4.2 at bus controller the at bus controller handles all of the at bus operations and dma/refresh arbitration. the controller has the following features: ? programmable at bus clock - the at bus clock, atclk, is selectable from either clk2/6 (default) or clk2/4. ? turbo switch - the 82C283 has a turbo swi tch feature allowing users to change the system clock speed. setting register 14h, bit 1 high (to 1), enables the turbo function, whereupon the 82C283 turbo pin selects the system clock speed as follows: - a low on the turbo pin causes the cpu to run at the current at bus speed (either clk2/6 or clk2/4). - a high on the turbo pin causes the cpu to run at 16, 20 or 25mhz. - if the keyboard controlled turbo switching is desired, the turbo pin should be kept low and the turbo configura- tion bit should be toggled. 4.3 sx/at system operation the detailed operation of an 82C283-based sx/at system design is descri bed in the following sub-sections. 4.3.1 reset the power supplys power good (pwrgd#) signal initializes the system when pwrgd# goes low. the 82C283 f orces cpurst, nprst high and sysrst# low, then negates these signals 128 clk2 cycles after pwrgd# goes high. 4.3.2 local dram interfaces local memory (dram) is located on the cpu local data bus. the cpu reads data directly from local memory. local mem- ory latches cpu write data on the leading edge of cas#. the memory controller asserts m16# when external master cards read local memory, and asserts dwe# when they write local memory. for parity control, the memory controller reads the requested byte(s) and checks parity; during local memory writes, the data bus control unit generates parity, to be stored in l ocal memory. 4.3.3 system bios rom if the system bios rom is not shadowed, rom cycles are treated as at cycles. 8-bit bios rom resides on the xd bus and 16-bit bios rom on the sd bus. with 16-bit rom, romcs# is connected to m16# through an open collector (a driver such as a 7407), allowing the 82C283 to determine the width of the rom data path by monitoring m16#. 4.3.4 i/o ports located on the xd bus xdir# controls the direction of i/o ports on the xd bus. not that i/o ports 0f0h-0ffh are reserved for the coprocessor. 4.3.5 refresh cycles the at bus controller arbitrates between the 82c206 hold request (hrq) and the 82C283 refresh re quest, to determine who receives bus control when the cpu relinquishes it. the bus controller grants refresh requests once every 15.9s (regular refresh) or once every 63.6s (slow refresh). during refresh, the at bus controller asserts rfsh# and memrd# and generates the refresh address. 4.3.6 dma cycles hrq initiates a dma/master transfer. when the 8 2c283 selects dma (via the hrq input) over the refresh request, after the cpu acknowledges by asserting hlda, then the 82C283 se nds hlda1 to the 82c206 to acknowledge the request. the 82c206 asserts dma16# and activates ads16# to start 16-bit dma transfers, or asserts dma8# and activates ads8# to start 8-bit dma transfers.
82C283 912-3000-012 page 11 opti ? 5.0 configuration registers there are seven configuration registers inside the 82C283. an indexing scheme is used to access all of these registers. port 22h is used as the index register and port 24h is the data register. each access to a configuration register con- sists of a write to port 22h, specifying the desired register in the data byte, followed by a read or write to port 24h with the actual register data. the index resets after every access; therefore every data access (via port 24h) must be preceded by a write to port 22h, even if the same register is being accessed on consecutive occasions. all reserved bits are set to zero by default. table 5-1 dram configuration register - index 10h bit(s) type default function 7 ro 0 82C283 revision number: 0 = revision a 1 = revision b 6 r/w 0 revision a: reserved - must always = 0. revision b: 0 = non-pipelined 1 = pipelined 5 r/w 1 local dram read cycle wait state: 0 = zero wait state 1 = one wait state 4 r/w 1 local dram write cycle wait state: 0 = zero wait state 1 = one wait state 3:0 r/w 1111 local dram memory confi guration: bits bank 0 bank 1 bank 2 bank 3 total 1111 256k 256k 1m 0001 256k 256k 256k 256k 2m 0010 256k 256k 1m 3m 0011 256k 256k 1m 1m 5m 0100 256k 256k 4m 9m 0101 2m 0110 1m 1m 4m 0111 1m 1m 1m 6m 1000 1m 1m 1m 1m 8m 1001 1m 4m 10m 1010 1m 1m 4m 12m 1011 4m 4m 16m 1100* 4m 8m *rev. b only
82C283 page 12 912-3000-012 opti ? table 5-2 shadow ram control register - index 11h table 5-3 shadow ram control register - index 12h bit(s) type default function 7 r/w 1 shadow ram enable for system bios rom at f0000h-fffffh: 0 = read only from shadow ram 1 = reads go to rom and writes go to shadow ram 6 r/w 1 adaptor rom located at e0000h-effffh: 0 = all accesses are to system board rom, shadow ram is disabled 1 = shadow ram is selectively enabled in 16kb blocks by cfg register 12h; other accesses are at bus cycles. 5 r/w 1 rom located at d0000h-dffffh: 0 = all accesses are on at bus and shadow ram is disabled 1 = shadow ram is selectively enabled in 16kb blocks by cfg register 12h; other accesses are at bus cycles. 4 r/w 1 rom located at c0000h-cffffh: 0 = all accesses are on at bus and shadow ram is disabled 1 = shadow ram is selectively enabled in 16kb blocks by cfg register 13h; other accesses are at bus cycles. 3 r/w 0 shadow ram copy enable control for c0000h-effffh: 0 = write to at bus 1 = write to local dram 2:0 r/w 000 shadow ram at x0000h-xffffh rea d/write status: 0 = read/write 1 = read only (while shadow ram is being loaded, this bit must be set to 0; after sha dow ram is loaded, setting this bit to 1 write-protects shadow ram.) bit 2 = e0000h -effffh bit 1 = d0000h-dffffh bit 0 = c0000h-cffffh bit(s) type default function 7:0 r/w 0000 0000 this register selectively enables shadow ram in 16kb blocks from d0000h-effffh. this and the shadow ram register (index 11h) implement full system selective shadowing. shadow ram for xx000h-xxfffh segments: 0 = disable 1 = enable bit 7 = ec000h-effffh bit 3 = dc000h-dffffh bit 6 = e8000h-ebfffh bit 2 = d8000h-d8fffh bit 5 = e4000h-e7000h bit 1 = d4000h-d7fffh bit 4 = e0000h-e3fffh bit 0 = d0000h-d3fffh
82C283 912-3000-012 page 13 opti ? table 5-4 shadow ram control register - index 13h table 5-5 miscellaneous control register - index 14h bit(s) type default function 7:4 r/w 0000 shadow ram for cx000h-cxfffh s egments: 0 = disable 1 = enable bit 7 = cc000h-cffffh bit 5 = c4000h-c7000h bit 6 = c8000h-cbfffh bit 4 = c0000h-c3fffh 3:0 r/w 0000 remap address for unused shadow ram. remaps a0000h-bff ffh and d0000h- effffh if not used for shadowing. bits 3 through 0 correspond to address 23 through 20. a23 a22 a21 a20 remap address 0000no mapping 00011mb 00102mb 00113mb 01004mb 01015mb 01106mb 01117mb 10008mb 10019mb 101010mb 101111mb 110012mb 110113mb 111014mb 111115mb bit(s) type default function 7 r/w 0 zenith mode: setting this bit to 1 will turn on the zenith mode which allows f0000h-f0fffh to be written while write-protect is on. 6 r/w 0 keyboard reset control: if active, a halt instruction must be exe cuted before the 82C283 gener- ates a cpu reset from the keyboard reset. 5 r/w 0 master byte swap enable. 4 r/w 0 rev. a: reserved - must be programmed to 0. rev. b: 0 = atclk set with register 14h, bit 0 (default) 1 = atclk = clk/8 for 33mhz operation 3: r/w 0 rev. a: reserved - must be programmed to 0. rev. b: 0 = disable on-board parity errors (main dram) (default) 1 = enable on-board parity errors (main dram) 2 r/w 0 slow refresh mode: the 82C283 refresh request is generated internally every 15.9s. setting this bit to a 0 will cause a refresh request to occur every 63.6s. 1 r/w 0 turbo switch function: turning on this bit enables the turbo switch function. 0 r/w 0 at clock select: 0 = atclk2 = cpuclk2/6 1 = atclk2 = cpuclk2/4
82C283 page 14 912-3000-012 opti ? 5.1 at compatible registers 5.1.1 i/o port 61h (port b) the 82C283 provides access to port b, i/o port address 61h defined for the pc/at as shown in table 5-6. at power-on, the nmi is disabled. however, it can be enabled or disabled by writing to i/o port 70h with data bit 7 equal to zero or one, respectively. an nmi occurs when nmi is enabled. if bits 3 or 2 are enabled, an iochck or pck occurs. table 5-6 port 61h (port b) bit(s) type function 7 r system parity check: this bit indicates that an on-board ram parity error has occurred. it can only be set if bit 2 (parity check enable) = 0. this bit should be cleared by writing a 1 to bit 2. 6 r i/o channel check: this bit indicates that a peripheral device is reporting an error. it can only be set if bit 3 (i/o channel check enable) = 0. this bit should be cleared by writing a 1 to bit 3. 5 r timer out2 detect: this bit indicates the current state of the out2 si gnal from the on-board timer. 4 r refresh detect: this bit is tied to a toggle flip-flop which is clocked by refresh. it toggles the opposite state every time a refresh cycle occurs. 3 r/w i/o channel check enable: when this bit is set low, it allows an nmi to be generated if the i ochck# input is pulled low. otherwise, the iochck# input is ignored and can not generate an nmi. 0 = enable 1 = disable 2 r/w parity check enable: when this bit is set low, it allows parity errors from on-board ram me mory to cause an nmi. when high, on-board ram parity errors will not cause an nmi. 1 r/w speaker output enable: this bit is gated with the output of counter 2 from the on-board timer. when this bit is high, it allows the out2 frequency to be passed out on the spkr pin. w hen low, the spkr output is forced low. 0 = enable 1 = disable 0 r/w timer 2 gate: this bit goes to the gate2 input of the on-board timer to enable counter 2 to produce a speaker frequency. 0 = enable 1 = disable
82C283 912-3000-012 page 15 opti ? 6.0 maximum ratings stresses above those listed in the following tables may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. 6.1 absolute maximum ratings 6.2 dc characteristics vcc = 5.0v 5%, ta = 0c to +70c group a pins: d[15:0], mp[1:0], rdyo#, atclk, ma[ 9:0], ras[3:0]#, cas[7:0]# group b pins; pclk2, sd[15:0], rfsh#, sa[19:17], smrd#, smwr# symbol parameter min max unit vcc supply voltage -0.5 6.5 v vi input voltage -0.5 vcc + 0.5 v vo output voltage -0.5 vcc + 0.5 v top operating temperature 0 +70 c tstg storage temperature -40 +125 c symbol parameter min max unit condition vil input low voltage -0.3 0.8 v vih input high voltage 2.0 vcc + 0.3 v vol output low voltage 0.45 v iol = 3.0ma all pins except: iol = 6.0ma for group a iol = 12.0ma for group b voh output high voltage 2.4 v iol = -1.6ma all pins except: iol = -3.2ma for group a iol = -3.2ma for group b iil input leakage current -10 10 a vin = vcc ioz tristate leakage current -10 10 a cin input capacitance 10 pf cout output capacitance 10 pf icc (20mhz) power supply current 50 ma
82C283 page 16 912-3000-012 opti ? 6.3 ac characteristics - 16/20/25mhz symbol parameter min max unit condition t1 rdyi# setup time to clk2 - 13 ns t2 rdyi# hold time to clk2 - 12 ns t3 cpurst active delay from clk2 - 017ns t4 cpurst inactive delay from clk2 - 512ns t5 rst4 active delay from clk2 - 017ns t6 rst4 active delay from clk2 - 017ns t7* nprst active delay from clk2 - 0 17 ns 30 pf load t8* nprst inactive delay from clk2 - 5 12 ns 30 pf load symbol parameter min max unit condition t11 busy# active delay from npbusy# 20 ns t12 busy# inactive delay from npbusy# 20 ns t13 nperr# se tup time to npbusy# 5 ns t14 nprst active delay f rom iow# 32 ns t15 nprst inactive delay from iow# inactive 32 ns symbol parameter min max unit condition t41 sd[15:0] setup time to iord# (memrd#) 22 ns t42 sd[15:0] hold time f rom i ord# (memrd#) 3 ns t43 sd[15:8] active delay from sd[7:0] valid 2 24 ns t44 sd[15:8] inactive delay from sd[7:0] invalid 2 24 ns t45 nmi active delay from chck# active 25 ns t46 sd[15:0] active delay from d[15:0] valid 2 25 ns t47 sd[15:0] inactive delay from d[15:0] invalid 2 25 ns t48 mp[1:0] active delay from d[15:0] valid 2 27 ns t49 mp[1:0] inactive delay from d[15:0] invalid 2 27 ns t50 d[15:0] active delay from sd[15:0] valid 2 25 ns t51 d[15:0] inactive delay from sd[15:0] invalid t52 d[15:0] active delay from sd[15:0] valid 2 27 ns t53 d[15:0] inactive delay from sd[15:0] invalid 2 27 ns symbol parameter min max unit condition t54 ale active delay from atclk - 015ns t55 ale inactive delay from atclk - 015ns
82C283 912-3000-012 page 17 opti ? t56 command active delay from atclk - 015ns t57 command inactive delay from atclk - 015ns t60 chrdy setup time to atclk 15 ns t61 chrdy hold time from atclk 5 ns t62 hold active delay from atclk 0 20 ns t63 hold inactive delay from atclk 0 20 ns t64 rfsh# active delay from atclk - 020ns t65 rfsh# inactive delay from atclk - 020ns t66 memrd# active delay from atclk - 020ns t67 memrd# inactive delay from atclk - 022ns t68 hrq setup time to atclk - 15 ns t69 hrq hold time to atclk - 20 ns t70 hlda1 active delay from hlda active 0 20 ns t71 hlda1 inactive delay from hlda inactive 0 20 ns symbol parameter min max unit condition t80 ras# active delay from xmemw# (xmemr#) active 0 22 ns t81 ras# inactive delay from xmemw# ( xmemr#) inactive 0 22 ns t82 ma[10:0] active delay from ras# active 0 22 ns t83 cas# active delay from xmemw# (xmemr#) active 20 40 ns t84 cas# inactive delay from xmemw# ( xmemr#) inactive 20 40 ns t85 dwe# active delay from xmemw# (xmemr#) active 20 40 ns t86 dwe# inactive delay from xmemw# (xmemr#) inactive 20 40 ns symbol parameter min max unit condition t90 cas# active delay from clk2 - 520ns t91 cas# inactive delay from clk2 - 520ns t92 rdy# active delay from clk2 - 420ns t93 rdy# inactive delay from clk2 - 420ns t98 ras# active delay from clk2 - 521ns t99 ras# inactive delay from clk2 - 521ns t100 ma[10:0] active delay from clk2 - 521ns t101 dwe# active delay from clk2 - 520ns t102 dwe# inactive delay from clk2 520ns symbol parameter min max unit condition ac characteristics - 16/20/25mhz (cont.)
82C283 page 18 912-3000-012 opti ? all ac specifications are relative to the clk2 rising/falling edge crossing the 2.0v level. all other signals are relative to their ris- ing/falling edge crossing 1.5v level. notes: 1. - means rising edge. 2. means falling edge. 3. loading capacitance is 50pf unless otherwise noted. clk2 period 20 ns clk2 high time 8 ns clk2 low time 8 ns clk2 fall time 4 ns clk2 rise time 4 ns symbol parameter min max unit condition ac characteristics - 16/20/25mhz (cont.)
82C283 revision: 1.0 912-3000-012 page 19 opti ? 6.4 ac timing waveforms figure 6-1 reset timing figure 6-2 numeric processor reset timing clk2 rdy1 cpurst (nprst) rst4 nprst f 1 f 2 f 1 f 2 f 1 f 2 t1 t2 t3 t5 t7 t10 t6 t4 npbusy# busy# iowr# nprst nperr# t11 t12 t13 t14 t15
82C283 page 20 912-3000-012 revision: 1.0 opti ? figure 6-3 data setup and hold time for iord# or memrd# figure 6-4 data valid and invalid delay between sd[15:8] and sd[7:0] figure 6-5 nmi valid delay related to chck#] iord# (memrd#) sd[15:0] t41 t42 sd[15:8] sd[7:0] t43 t44 nmi chck# t43
82C283 revision: 1.0 912-3000-012 page 21 opti ? figure 6-6 sd[15:0] to d[15:0] and mp[1:0] valid and invalid delay d[15:0] sd[15:0] mp[1:0] t46 t47 t49 t48 sd[15:0] d[15:0] mp[1:0] t50 t51 t53 t52
82C283 page 22 912-3000-012 revision: 1.0 opti ?
82C283 912-3000-012 page 23 opti ? 7.0 mechanical package outline figure 7-1 160-pin plastic quad flat pack (pqfp) symbol millimeter inch min nom max min nom max a1 0.05 0.25 0.50 0.002 0.010 0.020 a2 3.17 3.32 3.47 0.125 0.131 0.137 b 0.20 0.30 0.40 0.008 0.012 0.016 c 0.10 0.15 0.20 0.004 0.006 0.008 d 27.90 28.00 28.10 1.098 1.102 1.106 e 27.90 28.00 28.10 1.098 1.102 1.106 e0.65 0.026 hd 31.65 31.90 32.15 1.246 1.256 1.266 he 31.65 31.90 32.15 1.246 1.256 1.266 l 0.65 0.80 0.95 0.025 0.031 0.037 l1 1.95 0.077 u 0.08 0.003 q 010010 he e hd d a2 a1 u eb 0.13(0.005) m c l l1 q
82C283 page 24 912-3000-012 opti ?

▲Up To Search▲

Price & Availability of 82C283

	To Download 82C283 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .